This invention generally relates to the generation of pseudo-random, spreading, orthogonal and synchronization codes for use in wireless communications and encryption applications. In particular, the invention relates to a programmable code generator for generating code sequences.
New code division, multiple-access (CDMA) standards are being developed at a fast rate, and these new standards require increasingly complex pseudo-random noise and code sequence generation. Pseudo-random noise or pseudo-noise (PN) sequences are commonly used in direct sequence spread spectrum communication systems such as that described in the IS-95 specification (ANSI/TIA/EIA-95-B-1999) entitled xe2x80x9cMobile Station-Base Station Compatibility Standard for Wideband Spread Spectrum Cellular Systemsxe2x80x9d (1999), published by the Electronic Industries Association (EIA), 2500 Wilson Blvd., Arlington, Va., 22201.
The IS-95 specification and its derivatives incorporate CDMA signal modulation techniques to conduct multiple communications simultaneously over the same RF bandwidth. Each base station and user communicating with the base station in a CDMA system may employ individually assigned PN code sequences for spread-spectrum xe2x80x9cspreadingxe2x80x9d of the channels. The assigned PN code sequence is a sequence of a predetermined number of bits. For each user transceiver, the PN code sequence may be used to spread data transmitted by the transceiver and to de-spread data received by the transceiver.
Each bit-period, or phase transition, of the PN code sequence may be defined as a chip, which is a fraction of the bit-period for each data symbol. Consequently, the PN code sequence may be combined with the data sequence so as to spread the frequency spectrum of the data. In IS-95, for example, 64 chips represent one data symbol. Each user may also be assigned a different Walsh code to orthogonalize the spread communication channel.
Demodulation of a spread signal received from a communication channel requires synchronizing a locally generated version of the PN code sequence with the embedded PN code sequence in the spread signal. The synchronized, locally generated PN code sequence may be correlated against the received signal to extract the cross-correlation. The signal of the extracted cross-correlation is the de-spread data signal.
Details of a method for PN vector generation may be found in the patent entitled xe2x80x9cMethod and Apparatus for Generating Multiple Matched-Filter PN Vectors in a CDMA Demodulatorxe2x80x9d by G. F. Burns, EPO994573, published Apr. 19, 2000. Another example of a PN generator may be found in Q. Zou et al., xe2x80x9cFast Slewing Pseudorandom Noise Sequence Generator,xe2x80x9d WO 00/31622, published Jun. 2, 2000.
Prior art has many examples of more traditional code generators, all of them with code generators that are constructed by using dedicated hardware. The sole purpose of the dedicated hardware is to generate a particular type of code. State variables may be stored in dedicated flip-flops or registers, and read by a predetermined set of hardware blocks whose function is determined by the wiring of the blocks. Mathematical and logical manipulations performed by these blocks are reasonably fixed in the type and order of the operations. Although parameters can sometimes alter the function of the hardware, such as changing the mask of a PN generator, their functionality is essentially that of unchanged traditional, fixed-function dedicated hardware and circuits.
Although building code generators in dedicated hardware may result in a very low cost solution, hardware is not very flexible and after it is built, changes are not made easily. Also, dedicated hardware resources cannot be reused for other operations, for example, moving from PN code generation with linear feedback shift register (LFSR) PN hardware to Walsh code generation. This is especially true for a multi-mode receiver or transmitter where codes can be completely different, or not required at all in particular protocols. Dedicated hardware may not work well, for example, within a software-centric approach to a radio transceiver, as in a software-defined radio. If a receiver or transmitter is implemented in software, software-implemented code generation may also be preferred.
Because preferred CDMA platforms should be able to support old, new and future CDMA standards, a highly flexible PN sequence generator is needed. A flexible PN generation architecture must have a high throughput capability to be able to support higher rate PN and orthogonal sequences, and be able to slew or advance the state of the PN generator quickly. Often CDMA signal processing integrated circuits are being developed before the standards are finalized, and when the standards change after hardware has already been released, costly and time-consuming reworks may be required unless a flexible solution is available.
There continues to be a need for highly adaptable receivers and transmitters that can handle multiple protocols in a single piece of hardware. Emerging multi-mode receivers and transmitters must support multiple CDMA standards, for example, IS-95A/B, IS-2000, and 3GPP. Each of these CDMA protocols requires a different set of CDMA codes that must be generated and manipulated in different ways. Using separate hardware for each new protocol may not be cost-effective, adaptable or practical. Alternatively, performing the code generation in software on a general-purpose DSP may be difficult because of the extremely large MIPs (millions of instructions per second) requirements, power requirements that may exceed restrictions in portable devices, and limitations on clock frequency that may prevent it from generating the required code at sufficiently rapid rates.
A preferred code generator, in particular a PN code generator, would be flexible enough to support multiple standards, multi-mode receivers and transmitters, as well as orthogonal code generation on the same hardware. A preferred PN generator would accommodate the generation of many different types of spreading codes, for example, LFSR, maximal-length m-sequences, Gold sequences, and orthogonal covering codes such as Walsh or orthogonal variable spreading factor (OVSF) codes. It would accommodate the increased lengths and parallel code-generation requirements that are limited by fixed hardware. The code-generation unit would support other special purpose codes, such as synchronization codes. The code-generation architecture would allow extended length PN sequences and parallel generation of code chips, with consideration for low power consumption, low voltage, low operating frequencies, and code-generation rate requirements.
The object of this invention, therefore, is to provide a method and a system for high throughput code generation, with a high level of flexibility to generate varied codes in CDMA and multi-protocol systems, and to overcome the deficiencies and obstacles described above.
One aspect of the invention provides a method for generating a code sequence, including the steps of receiving a code-generation instruction, determining control signals based on the code-generation instruction, and generating the code sequence based on the control signals, a current state input, and a mask input.
The generated code sequence may be a spreading code, a covering code, an orthogonal code, a synchronization code, a pseudo-noise code, a slewed pseudo-noise code, an arbitrary-length pseudo-noise code, an m-sequence code, a Walsh code, an orthogonal variable spreading factor code, a Gold code, a 3GPP hierarchical code, a frequency-corrected code sequence, a user-defined code sequence, or a predefined code sequence. The code-generation instruction may be a logic instruction, an arithmetic instruction, a shift instruction, a rotate instruction, a move instruction, a pack instruction, an unpack instruction, a flip instruction, a load instruction, a pseudo-noise generate instruction, a multiple pseudo-noise generate instruction, a Walsh generate instruction, or a multiple Walsh generate instruction.
A set of terms for a next state input may be generated based on the control signals, the current state input, and the mask input. A plurality of intermediate terms may be stored in a register file, and M sequential bits of a specified pseudo-noise code sequence may be generated, where M is the length of the generated pseudo-noise vector. Multiple elements of a code sequence may be generated in parallel, based on the control signals, the current state input, and the mask input.
Another aspect of the current invention is a code-generation system, containing a means for receiving a code-generation instruction, a means for determining control signals based on the code-generation instruction, and a means for generating the code sequence based on the control signals, a current state input, and a mask input.
The system may contain a means for generating a set of terms for a next state input based on the control signals, the current state input, and a mask input. The system may also contain a means for storing a plurality of intermediate terms in a register file, and a means for generating M sequential chips of a specified pseudo-noise code sequence, wherein M is a length of a generated pseudo-noise vector. The system may contain a means for generating multiple elements of a code sequence in parallel based on the control signals, the current state input, and the mask input.
Another aspect of the current invention is a code-generation system, comprising an instruction memory, an instruction decoder connected to the instruction memory, a code-generation arithmetic logic unit connected to the instruction decoder, and a register file connected to the instruction decoder and the code-generation arithmetic logic unit, where code may be generated by the arithmetic logic unit from a current state input, mask input from the register file, and control signals that are determined by the instruction decoder based on an instruction received from the instruction memory.
The code-generation system may include a temporary storage register, where results from several arithmetic logic unit operations may be stored. The code-generation system may include a carry register, where intermediate results from the code-generation arithmetic logic unit may be stored. The code-generation system may include a correlation arithmetic logic unit connected to the code-generation arithmetic logic unit, where code may be transferred to the correlation arithmetic logic unit from the code-generation arithmetic logic unit. The code-generation system may include one or more general-purpose arithmetic logic units connected to the register file, where the resources of the register file may be shared between the general-purpose arithmetic logic units and the code-generation arithmetic logic unit.
Another aspect of the current invention is a method for generating code comprising selecting a code type, generating a plurality of instructions based on the selected code type, and storing the instructions in a code-generation instruction memory. The code-generation instruction memory may be located in a multi-mode transceiver. The code-generation instruction memory may be located in an encryption device.
Another aspect of the current invention is a computer usable medium including a program for generating a code sequence for selecting a code type, for generating a plurality of instructions based on the selected code type, and for storing the instructions in a code-generation instruction memory. The computer program code may reside in a software-defined radio.
Another aspect of the current invention is a programmable code-generation system, including a means for selecting a code type, a means for generating a plurality of instruction based on the selected code type, and a means for storing the instructions in a code-generation instruction memory.
The aforementioned, and other features and advantages of the invention will become further apparent from the following detailed description of the presently preferred embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the invention rather than limiting, the scope of the invention being defined by the appended claims and equivalents thereof.